Thin film transistors, hereinafter referred to as "TFT", are widely used in liquid crystal display (LCD) devices and other microelectronic applications. In general, a TFT liquid crystal display includes a thin film transistor array substrate, a spaced apart color filter substrate and a liquid crystal material therebetween. The thin film transistor array substrate includes an array of thin film transistors, electrodes and signal lines.
Referring now to FIG. 1, a conventional TFT used for an LCD will now be described. As shown in FIG. 1, a gate electrode 12 is formed on the substrate 10 and a gate insulating layer 14 is deposited thereon. An amorphous silicon layer 16 is formed on the gate insulating layer 14. The amorphous silicon layer 16 operates as a channel for the thin film transistor.
A highly doped amorphous silicon layer 161, for example an n+ doped amorphous silicon layer 161, and a silicide layer 18 are formed on the gate insulating layer 14. A chromium layer 181 is formed on the silicide layer 18, to provide source/drain electrodes. The silicide layer 18 is generally formed of chromium silicide, which is formed by reaction of the n+ amorphous silicon layer 161 and the chromium layer 181. As is well known, the silicide layer 18 in combination with the n+ amorphous silicon layer 161, improves the ohmic contact between the channel layer 16 and the source/drain electrodes.
Unfortunately, in the TFT of FIG. 1, the source/drain electrodes may include an open near the edge of the gate electrode 12, due to the topological difference between the substrate 10 and the gate electrode 12. Moreover, the chromium layer 181 which acts as the source/drain electrode, may have high resistivity, which may increase the delay in the thin film transistor and degrade its performance.
In order to overcome the above problems, double layer source/drain electrode structures have been suggested. In particular, the double layer structure includes a layer of relatively high resistivity and a layer of relatively low resistivity. Accordingly, the net resistivity of the source/drain electrodes may be lowered and open circuits at the source/drain electrodes may be reduced.
For example, as shown in FIG. 2, a lower layer 281 is formed of chromium which is silicidable but which has a high resistivity. An upper layer 282 is made of aluminum which is not silicidable, but which has relatively low resistivity. The lower part of the lower layer 281 is silicided to form a silicide layer 28.
FIG. 3 illustrates another example of a TFT which can provide lower resistivity. As shown in FIG. 3, a lower layer 381 is formed of aluminum and an upper layer 382 is formed of chromium. Since the lower layer 381 is not silicidable, a silicide layer is not formed.
In the TFTs of FIGS. 2 and 3, since the source/drain electrode include two-layer structures, the likelihood of open circuits near the edges of the gate electrode 12 is reduced. Moreover, since one of the two layers is made of aluminum, which has a lower resistivity than chromium, the net resistivity may be lowered.
Unfortunately, in the TFT of FIG. 2, since aluminum may be easily oxidized, defects may occur near the edge of the TFT panel where the aluminum is exposed. Also, in the TFT of FIG. 3, since the lower layer is in direct contact with the n+ amorphous silicon layer 161, the ohmic contact between the amorphous silicon layer 16 and the source/drain electrodes may be degraded. Accordingly, notwithstanding the improvements of FIGS. 1, 2 and 3, there exists a need for further improvements in TFT structures and fabrication methods.